It’s Java source to C source translator, which allows to write MCU firmware in Java.

“yes”  

Key features

  • Source code is written in Java, not C.
  • Source code is translated to C source code, which is compiled and programmed to target device. MCU doesn’t interpret anything.
  • No manual register handling needed! Write, for example, timer.setMode(TimerMode.FAST); instead of inconvenient TCCR1B |= (1<<WGM12); TCCR1A |= (1<<WGM10); Register handling is done automatically by MCU Java Source. Now you need to keep in mind only the principle of operation of MCU devices (timers, UART, ADC), but not registers and bits.
  • MCU register initialization on startup is done separately in init() function and is highly optimized.
  • MCU internal devices (e.g. timers) are represented as Java objects.
  • Interrupts are represented as object’s listeners (e.g. ExternalInterruptListener, TimerCompareListener). Of course, methods addXxxListener() also work.
  • UART uses input and output streams, as usual in Java.
  • User objects
  • Handy documentation (Javadoc) for all available objects and methods (functions).
  • Before translation source code is compiled by Java compiler. This prevents many errors.
  • For highly device-optimized applications, it is possible to work with register directly through Register class, unless there is another way to do needed action.
  • New MCUs and even platforms can be added, if C compiler supporting it exists.

What it is and is not MCU Java Source is:

  • Tool that allows to write MCU programs in Java.

MCU Java Source is not:

  • JVM (Java Virtual Machine) for MCU. All java code is translated to native at source level, then compiled to machine code.
  • Tool for AVR32 with hardware JVM. This program is not for high-end MCU’s.

Supported MCU platforms/devices

AVR Compiler – avr-gcc (or WinAVR package)

  • ATmega8
  • more will be added

Java source code elements

Supported (implemented) now

  • final. Primitive fields with final attribute turn to #define declarations. Strings and primitive arrays are put to program memory and got from it when they are used. No manual working with progmem – just make a field final!
  • Listeners. Only interrupt listeners are supported. Interrupt listeners turn to interrupt service routines.
  • Variables/fields. Only primitive (and primitive array) variables are passed to C source, MCU Java source object handling is interpreted by translator, user object are not supported now.
  • volatile is passed to C source. Use it when variable is used in background thread and interrupt.
  • byte and boolean types are supported throught typedef unsigned char.
  • I/O. InputStream and OutputStream classes are used in UART. Since charset enconders/decoders don’t fit into MCU, only default charset is used. That’s why there’s no BufferedReader, BufferedWriter classes, instead BufferedInputStream, BufferedOutputStream are used.
  • User objects
  • External device library (partially):
    • Multi digit LED display
    • Character LCD
    • Nokia 3310 LCD

Not yet implemented

  • External device library (partially implemented). For example, I2C EEPROM, temperature sensor.
  • Anonymous classes and statement like method(new MyListener())
  • Static initializers and instance initializers will be added to start() function
  • @Section annotation. Will specify, where to put final variables – Flash or EEPROM memory. Now Flash by default. Example:

    @Section(Section.EEMEM)
    private static final String MESSAGE = “Hello, EEPROM!”;

  • Two-threaded model: background thread and interrupt (Event Dispatch) thread. Task (implements Runnable) like in TinyOS 2.0. Tasks will be executed in background thread and posted from anywhere.
  • Simulator: Java source can also be compiled and run on computer. So, program will be simulated.

No way to do it

  • synchronized is completely ignored. Use volatile instead.
  • Exceptions. Native code don’t support them.
  • static is completely ignored because C has different meaning of it.

System requirements

  • Windows or Linux
  • Java 6 JDK

How it works

Java source code is converted to XML representation (java-ml) using modified version of Java2XML. Then every XML element is processed by MCU Java Source Translator. All primitive variables don’t change, all objects are translated. For translation of methods dealing with MCU registers, there is separate translator for each MCU. All listeners are converted to interrupt handlers. Classes of user objects are not processed using XML, they are called using reflection. The result of translation is XML representation of C source code for MCU. Then C source is generated from XML.



 

At the Arab Museum of Modern Art in Doha, Qatar, Chinese artist Cai Guo-Qiang put on his largest ‘explosion event’ of the last three years, utilizing microchip-controlled explosives to form incredible designs and patterns. The video shot of the event is an impressive testament to how a volatile black powder explosion can be controlled and shaped by computers and microcontroller technology.

 
 

8,300 (206Chex) microcontrollers blast in the air

Computer controlled daytime pyrotechnics show paints the sky

 

 

Each set of explosions was calculated to paint a different picture. One series of explosions created black smoke clouds that looked like “drops of ink splattered across the sky.” In another, 8,300 shells embedded with computer microchips exploded in a pyramid shape over the desert.

Youtube Video link:
http://www.youtube.com/watch?v=FPV8zdiySlI

I was thinking of learning FPGA, although my college lab have plenty of FPGA boards I want to buy one board for my needs. FPGA Boards are very costly. Relative to the microcontrollers FPGA board and the softwares both are 5 times more priced. The sad thing is that in FPGA world there is no free or opensource software for the whole thing. Either you have to use pirated version or Buy a Development board to get a Hardware locked Software Pack. Hardware locked means these pack can be used program only that class of development boards.

Another thing is that if someone want to design a board himself ? is it possible

Yeah its possible, but there is not so much help on the web, But there are some open hardware projects like the XULA Board from Xess Corp.

Xula Board

Xula board uses altera Cyclone IV with 32,000 Logic elements and support for VGA, Now Xula board is produced by some other companies also, available in ebay, digikey…

DE0

DE0 is another lowcost FPGA board for beginners using altera Cyclone IV, people had tried Linux on it. There is two new modified version DE0 Nano and DE4.

Papillio

Papillio is an open hardware project equivalent to Auridino project . The auridino was for microcontrolles and this is for FPGA world. It has equivalent peripheral component blocks like the Auridino Peripheral boards. Papillio hardware is marketed by Digikey, Avnet and other worldwide distributers.

The Basic Architechture

As the FPGA chips have no static memory each time it is powered on the configuration data need to be reloaded by some interface. So the common devlopement board contains a micro controller for this job. Another necessary thing is a interface to computer , if the microcontroller has USB support then it is enough otherwise we need a USB chip like the FTDI. Some Devlopment board vendors also provide a ethrnet interface both for application and Bitstream(configuration data) loading purpose.

 

Board Block Diagram Xula

Am still confused about which one to start with ….

Parallel port is basic need for hardware engineers involved in Microcontroller, FPGA or DATA Acquisition Projects. But now the PC Assembler companies (Lenevo, Dell) are not giving an parallel port in the system. Few other companies have the port on motherboard not in the back panel. Parallel port is laptop is very rare, I have seen this some of the oldest laptops, (my professor has one like this). The laptops have only USB, HDMI, VGA and RJ45. But they forgot our need the serial port and the Parallel Port.

Parallel Port is the simplest media to interface your project to the computer. Serial is the next simplest interface. But our systems lack both of these ports. So we need some alternative way to get a port on our system. The first option is a USB to parallel convertor or adaptor but these USB adaptors does not work for all purpose but only for printers. They virtualize a printer port. The USB to Serial works good for all purpose.

The PCMIA based parallel port is a real parallel port it works good. But PCMCIA card is not suitable for all. Some laptops don’t allow this.

So here is a option for you.

 

Source: http://www-user.tu-chemnitz.de/~heha/bastelecke/Rund%20um%20den%20PC/USB2LPT/index.html.en

Although I have not tested it but the description seems it will work for all things. Here they Compared with other methods like PCI card , PCMCIA Card based parallel ports with this converter.

Some Pros and Cons of this USB to parallel converter

  • + Emulated true parallel port with ECP/EPP
  •  Reduced speed due to emulation (expect 10..100 times slower)
  • + Base address same as built-in (378h, 278h)
  •  Doesn’t work with programs that expect a true PnP driver stack (scanners, ZIP drives) and software that disables port access redirection (dongles)
  • + Additional USB->ParallelPrinter adapter built-in (High-Speed only)
  • + USB available everywhere
  •  Driver necessary
  •  Driver unstable, tricky, not certified, and currently non-functional for Win64, currently no driver for Linux
  • + open-source, multi-language

Tested in Programmes listed below:

  • AVRdude
  • winPIC
  • AVR ISP
  • PonyProg
  • Xilinx Impact
  • AD9834 Analog devices
  • LabView
  • Matlab
  • And many more things

Hi buddies, am now free to write about the khata mitha experience at this institute.

After our 3rd semester was over we were not fully relaxed as there were still some burdens concerning the academics. We had to show the Prototypes of Minor Projects and seminar talk on the same. But my project was still not completed. In the meantime we had to search for a guide for our M.Tech. Thesis. I mailed all my seniors about my need. All of them are continuing SRF, Ph.D., PDF at their respected institutes. They all replied positively but due to some official restrictions I had to leave the choice. Besides this I had also mailed to number of professors from some NIT, IISc, IUAC and TIFR for some specific projects which are suitable for me. They all accepted my proposal but none of them provided accommodation which was necessary for me.I was in search of a senior person as my guide, but not so senior that he would not spare a hour in a week for me. For this I left all the chances.

CSIO, yeah this was the last option for all of us. So at last I decided to join project work at CSIO, as I had seen from a presentation by one of my seniors that there was some work going on E-nose on which I had worked a little.

Leaving H9 NIT Kurukshetra, shifting to Chandigarh

Nine of my classmates applied for CSIO (Me, Yogesh, Anoop, Sharad, Naveen, Gaurav, Manoj Tanwar, Jai, Ramamurthy ), there were two girls from MTech nano stream. We all shifted to a PG Hostel at Chandigarh on 28th dec.

Naveen Arranging Things in the PG Room at Chandigarh, Tiifin supplied by the PG owner

Anyway we got hostel room after some days so we shifted to the hostel. All of us got new roommates except yogesh, manoj and naveen. And then it was time to think about the project and the lab. We are three from NIT are joined for one single project in the agrionics lab(all of us are using different techniques).

U may have seen worst

Anyway we enjoyed a lot, Visited Jammu, Kasauli.. celebrated holi.. and …

 

“ARM” you must have heard about this fastest growing family of Microprocessor architecture. Every modern handset uses at least one ARM processor. In daily life you must have using 4/5 of these processors in bike/car, elevator, shop..and many more. As an embedded engineer 8bit or 16bit processors are not enough we have to learn the ARM 32 and there is another reason that we should work on the current technology which would pay us.

Now after completion of thesis (yet not M.Tech.) am jobless so trying to explore the ARM architecture. Writing this blog as a discussion / tutorial, if you wish you may co-author this. I will explain as I have proceeded yet through the domain.

Content

  • History
  • ARM Cores
  • ARM Manufactures and Products
  • Compilers and assemblers
  • “Hello World” on a ARM
  • Tutorials, Links, Forums

ARM is the leading provider of 32-bit embedded microprocessors, offering a wide range of processors based on a common architecture that deliver high performance, industry leading power efficiency and reduced system cost. Now its gained popularity in amateur projects also. ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine.

Acorn Computer (who is famous for the BBC Micro) was in need of a number of second processors to support BBC Micro, processors from Motorola and national was not enough for GUI. They tested all available and then they planned for their own processor ( Berkely RISC Project). They felt if a graduate student can design a 32 bit processor the why not Acorn. They started from western design center (Phoenix) and learnt that they don’t need massive resource and facilities. They simulated their Processor design with BBC Basic on a BBC Micro working with 6502 2nd Processor. They collaborated with  VLSI Technology, Inc was as a silicon partner, since it already supplied Acorn with ROMs and some custom chips. The design was led by Wilson and Furber, with a key design goal of achieving low-latency input/output (interrupt) handling like the 6502. The 6502’s memory access architecture had allowed developers to produce fast machines without the use of costly direct memory access hardware. VLSI produced the first ARM silicon on 26 April 1985 – it worked the first time and came to be known as ARM1 by April 1985. The first “real” production systems named ARM2 were available the following year.

The ARM2 featured a 32-bit data bus, a 26-bit address space and twenty-seven 32-bit registers. Program code had to lie within the first 64 Mbyte of the memory, as the program counter was limited to 24 bits because the top 6 and bottom 2 bits of the 32-bit register served as status flags. The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors(compare the transistor count with Motorola’s six-year older 68000 model which was aptly named, since it contained 68,000 transistors). Much of this simplicity comes from not having microcode (which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including any cache. This simplicity led to its low power usage, while performing better than the Intel 80286. A successor, ARM3, was produced with a 4 KB cache, which further improved performance.

ARM Cores

Architecture

Family

ARMv1

ARM1

ARMv2

ARM2, ARM3

ARMv3

ARM6, ARM7

ARMv4

StrongARM, ARM7TDMI, ARM9TDMI

ARMv5

ARM7EJ, ARM9E, ARM10E, XScale

ARMv6

ARM11

ARMv7

Cortex

To be Continued …


 

During my thesis works, I found the necessity of DSP and FPGA, so I had learned a bit of both and now I want to buy kit of either FPGA or DSP.

I have searched in various forums about this, here is the summary from edaboard

Q: Hi,
I’ll start working in February and I was asked to choose between working with FPGA(VHDL) or DSP(systemC). Please tell me what’s more interresting?
Thanks

ANS1:DSP is a processor but FPGA is array of gates.
DSP is a optimized processor for digital signal processing and fast processing. but fpga is suitable for boolon functions.

 

ANS2:I find FPGAs a lot more fun/useful/challenging than DSP chips. I started using DSPs about 15 years ago, building various array signal processors and controllers. About 5 years ago I dropped them and switched to Xilinx FPGAs. Enormously faster, more flexible, and less expensive than DSPs. However, many engineers find FPGA HDL more difficult to learn than DSP C/Assembler. An engineer with only software skills probably should not attempt FPGA unless you wish to learn a new career, because to create good FPGA designs you have to think like a digital hardware designer.

 

ANS3:FPGA is a trend of digital R&D, which focus on digital circuit realized in soft code but hardware thinking.
DSP’s famours charactor is it’s data stream processing.
Now, EE need to know the FPGA and DSP even the RISC MPU, ADC, DAC etc….

For DSP users have to implemente algorithm (s/w code) in efficient way (some arm’s programmer might focus on porting code for application/peripheriial rather than for cpu/core); selection of core/model and study of computation standards would be encourted oftenly.

but FPGA, as its high flexibility, one would consider to the system view. I think both them are very chanlleging……..

 

FPGAs have several significant advantages over high-end DSP processors. According to benchmark results (shown in Figure , for example, have shown that high-end, DSP-oriented FPGAs have a huge throughput advantage over high-performance DSP processors for certain types of signal processing. And FPGAs, which are not constrained by a specific instruction set or hardwired processing units, are much more flexible than processors.


Figure: Results of the BDTI Communications Benchmark (OFDM)™

The Two Solutions

The DSP is a specialised microprocessor – typically programmed in C, perhaps with assembly code for performance. It is well suited to extremely complex maths-intensive tasks, with conditional processing. It is limited in performance by the clock rate, and the number of useful operations it can do per clock. As an example, a TMS320C6201 has two multipliers and a 200MHz clock – so can achieve 400M multiplies per second.

In contrast, an FPGA is an uncommitted “sea of gates”. The device is programmed by connecting the gates together to form multipliers, registers, adders and so forth. Using the Xilinx Core Generator this can be done at a block-diagram level. Many blocks can be very high level – ranging from a single gate to an FIR or FFT. Their performance is limited by the number of gates they have and the clock rate. Recent FPGAs have included Multipliers especially for performing DSP tasks more efficiently. – For example, a 1M-gate Virtex-II™ device has 40 multipliers that can operate at more than 100MHz. In comparison with the DSP this gives 4000M multiplies per second.

Where They Excel

When sample rates grow above a few Mhz, a DSP has to work very hard to transfer the data without any loss. This is because the processor must use shared resources like memory busses, or even the processor core which can be prevented from taking interrupts for some time. An FPGA on the other hand dedicates logic for receiving the data, so can maintain high rates of I/O.

A DSP is optimised for use of external memory, so a large data set can be used in the processing. FPGAs have a limited amount of internal storage so need to operate on smaller data sets. However FPGA modules with external memory can be used to eliminate this restriction.

A DSP is designed to offer simple re-use of the processing units, for example a multiplier used for calculating an FIR can be re-used by another routine that calculates FFTs. This is much more difficult to achieve in an FPGA, but in general there will be more multipliers available in the FPGA. 

If a major context switch is required, the DSP can implement this by branching to a new part of the program. In contrast, an FPGA needs to build dedicated resources for each configuration. If the configurations are small, then several can exist in the FPGA at the same time. Larger configurations mean the FPGA needs to be reconfigured – a process which can take some time.

The DSP can take a standard C program and run it. This C code can have a high level of branching and decision making – for example, the protocol stacks of communications systems. This is difficult to implement within an FPGA.

Most signal processing systems start life as a block diagram of some sort. Actually translating the block diagram to the FPGA may well be simpler than converting it to C code for the DSP.

Power hungry FPGA
Energy efficiency is often a critical metric for signal processing applications. Battery-powered products are highly sensitive to energy consumption, and even line-powered products are often sensitive to power consumption, though it may be on a per-channel or per-unit-area basis. FPGAs have long been viewed as too power-hungry for most DSP applications, but we believe that this may be an obsolete perspective.

FPGAs use highly flexible architectures, and this flexibility is perhaps their greatest advantage. But flexibility comes with a hardware cost. More flexibility generally means more gates, more silicon area, more routing resources—and higher energy consumption. For this reason, FPGAs are generally less energy efficient than chips with dedicated hardware, such as ASICs.

But how do FPGAs compare to DSP processors? DSPs are highly tailored for efficient implementation of common DSP tasks, and thus many engineers assume that they are more energy-efficient than FPGAs. But DSP processors have their own inefficiencies. In a DSP, only a tiny fraction of the silicon is devoted to computation; most of the silicon area and most of the energy is devoted to moving instructions and data around. Hence, it would be a mistake to assume that FPGAs are inherently less energy efficient than DSPs.

In some high-performance signal processing applications, for example, FPGAs can take advantage of their highly parallel architectures and offer much higher throughput than DSPs. As a result, FPGAs’ overall energy consumption may be significantly lower than that of DSP processors, in spite of the fact that their chip-level power consumption is often higher.

Unfortunately, there is a dearth of accurate, apples-to-apples energy consumption data for FPGAs and DSP processors, making it difficult to compare their energy efficiency As part of the analysis for our recent report comparing FPGAs to DSPs, “FPGAs for DSP, 2nd Edition,” BDTI did its own “back of the envelope” comparisons of the energy efficiency of FPGAs and DSPs. Based on anecdotal data about FPGA power consumption, we estimated that high-end FPGAs implementing demanding DSP applications, such as that embodied in the BDTI Communications Benchmark (OFDM)™, consume on the order of 10 watts, while high-end DSPs consume roughly 2-3 watts. Our benchmark results have shown that high-end FPGAs can support roughly 10 to 100 times more channels on this benchmark than high-end DSPs, suggesting that their energy consumption per channel is significantly lower than that of DSPs. This contradicts the common view that FPGAs are energy hogs.

Obviously our comparison is based on very rough estimates. While we believe that FPGAs’ energy efficiency is likely to be competitive—or even superior—to that of DSPs in many high-performance signal processing applications, this is still an open question. What’s needed is a rigorous, well-controlled analysis of power consumption under comparable conditions.

Furthermore, the above analysis is only meaningful in the context of high-performance signal processing applications. Estimating the relative energy efficiency of FPGAs and processors for less-demanding signal processing applications would require a slightly different benchmarking approach and the evaluation of different chips (e.g., lower-power processors and smaller FPGAs); this is another area that’s ripe for further investigation.

 

Reference:

eetimes.com/design/signal-processing-dsp/4017003/FPGAs-vs-DSPs-A-look-at-the-unanswered-questions

hunteng.co.uk/info/fpga-or-dsp.htm

Everything changing, but the world of computer is changing at great pace. The architecture , overall size, processing speed, the languages…. In every dimension the things are changing. But we don’t care about all these updates except the legacy ports, the serial port and the parallel port. The serial port and the the parallel port are the basic interfacing mediums to interface our hardware module to a personal computer. With the introduction of new communication packet based protocols like USB, firewire, IEEE484(GPIB), SMBUS the legacy ports are replaced with these new ones.

So now the minimum requirement for your hardware module is USB connectivity. This can be done in three ways(ascending order of complexity)

  • Using USB to serial module
  • Using a USB supported microcontroller
  • Creating USB interface in your microcontroller

 

In the first method you need not to write driver for any side(neither host nor client), just connect and use as a normal COM Port. These modules come in different shapes and price of the module is INR 200/- to INR400/- . I had brought one from sector 20C Chandigarh at INR 250/-. In my lab am using another one from moxa which is using TUSB3410(USB microcontroller) from texas instruments. You can also make this one (as the second method in the above list) but you need to write the drivers for both sides.

A USB to serial module using FTDI chip

A USB to serial schematic with FTDI chip(http://electronics-diy.com/electronic_schematic.php?id=565)

USB connectivity categorized to three main categories

  • USB Host
  • USB Client
  • Both USB Host & Client

A personal computer works always as a USB Host.

The requirements for creating a USB client

  • USB client driver in your hardware
  • USB communication Hardware or an Software alternative of the same(USB library or firmware)
  • USB driver at Host(PC) for your USB device

The second requirement in the list is the important one all the links below will direct you to the pages where discussion is going on about this.

http://www.fourwalledcubicle.com/LUFA.php

http://savannah.nongnu.org/projects/avrusb/

http://www.beyondlogic.org/usb/usbhard2.htm

USB IR: http://www.codeproject.com/KB/miscctrl/USB_IR_with_c8051.aspx

http://www.tinyos8051wg.net/node/libraries

EZUSB:

http://www.linux-usb.org/ezusb/

http://ezusb2131.sourceforge.net/

VUSB / AVRUSB :

VUSB is the best opensource usb driver for atmel AVR series microcontrollers with minimum code space 2K (driver code size 1256 bytes), only one interrupt pin required for operation.

FTDI: I don’t like it

Reference: lvr.com/usbcode.htm (List of driver libraries)

intranet.daiict.ac.in/~ranjan/esp2007/presentation/t.pdf

obdev.at (VUSB official page)

Vector network analyzer: n2pk.com, scottyspectrumanalyzer.com

I can think of two types of frequency multiplier.

The first uses an amplifier that is deliberately driven into distortion so that a complex waveform is produced.

This will contain output on multiples of the input frequency.

Tuned circuits are then tuned to the required harmonic to recover this harmonic and reject others.

This is typically done in receivers and transmitters where a known stable signal is available but a multiple of that frequency is needed as a local oscillator for a mixer.

The other type of frequency multiplier is one that uses a free running oscillator near the desired high frequency. This oscillator frequency is divided by some exact amount using a digital divider.
This divided down signal is then compared with a known reference in a phase comparator and an error signal is sent back to the oscillator to pull it onto an exact multiple of the reference signal.

I also saw a reference to someone multiplying the frequency of a red laser to get green laser output. I have no idea how they did that.

———————————————————————————

Reference: physicsforums.com/showthread.php?t=343272